As an external storage device used in a computer system, an SSD (Solid State Drive) mounted with a nonvolatile semiconductor memory such as a NAND-type flash memory attracts attention. The flash memory has advantages such as high speed and lightweight compared with a magnetic disk device. The SSD includes therein a plurality of flash memory chips, a controller that performs read/write control of each flash memory chip corresponding to a request from a host device, a buffer memory for performing data transfer between each flash memory chip and the host device, a power supply circuit, a connection interface for the host device (for example, Patent Document 1: Japanese Patent No. 3688835).
When data is stored in a nonvolatile semiconductor storage element such as a NAND-type flash memory, writing is performed after once erasing data in units of so-called block, reading/writing is performed in units of so-called page, or a unit of erasing/reading/writing is fixed. On the other hand, a unit of reading/writing of data from/to a secondary storage such as a hard disk by a host device such as a personal computer (PC) is called a sector. The sector is set independently from a unit of erasing/reading/writing of a semiconductor storage element. Typically, a size of the block, the page, and the sector has a relationship of block>page>sector.
In this manner, a unit of erasing/reading/writing of a semiconductor storage element is larger than a unit of reading/writing of a host device in some cases. When a secondary storage of a PC such as a hard disk is configured by using such a semiconductor storage element, small size data from the PC as the host device needs to be subjected to an address translation after conforming to a block size and a page size of the semiconductor storage element.
Moreover, when a secondary storage with a large capacity is configured by using such a flash memory, a cache memory is often interposed between the flash memory and a host device to reduce the number of times of writing (the number of times of erasing) in the flash memory as described in Patent Document 2 (Japanese translation of PCT international application No. 2007-528079).